Right. The real jump from small to large RAM devices is the presence or absence of DRAM.

Large SRAMs get costly and power hungry quick - the largest RAM Cortex-M4 devices have about 192KiB of SRAM, but cost $6-10. The jump to DRAM, however, is very expensive, because DRAM is fabricated on a different process and needs to be installed as a separate die or package. It is also too high latency to use as the only RAM, so a SRAM cache is still necessary.

The market currently segregates a lot of other features based on the RAM interface. Cortex-M series cores, sold as "microcontrollers", almost never have DRAM, only support Thumb-2, and have no MMU. Cortex-A series are sold as "application processors", have external DRAM interfaces, and include a MMU. A similar divide is visible with the MIPS architecture.

Even adding a large dram using a different die is quite cheap. there's a $2 feature phone chip with CPU + 8MB dram die.

And integrating 2 dies in general isn't that expensive ,I've see small micros integrated with a power die for $1.5 .

Its mostly about business and politics like the parent says.

I'm starting to see more and more Cortex-Ms with DRAM interfaces. STM32F427s added them to their FSMC peripheral (their new discovery board has 32MB of DRAM actually).

NXP's LPC line of microcontrollers are M3 or M4-based and have external SDRAM interfaces that work pretty well (no high-speed layout necessary). They've been around for a while.

> 8051 was ~60K transistors (same ballpark as Cortex M4)

While I agree with your overall premise, could you provide a citation on this? I find it hard to believe that a Cortex M4 is only 60K transistors. A 32x32 multiplier should be almost 10,000 transistors by itself.

Cortex M0+ is 12k gates in it's smallest configuration according to http://www.arrownac.com/offers/nxp-semiconductors/cortex/cor...

This page quotes a Cortex M4 announcement press release (which I can't find) which says that a stock M4 (without FPU/DSP instruction support) comes in at 65k gates. Meanwhile this pdf: http://www.mcu-related.com/architectures/35-cortex-m3/96-cor... claims that an M3 comes in at 43k gates. The main difference between the two is a 32x32+64 into 64 multiplier for DSP use plus some SIMD instructions so your estimate for the multiplier seems to be in the right ballpark!

Counting gates vs transistors is about a factor of four or more difference.

You're right, I'd missed that - I imagine that would probably explain the confusion in the parent post then!

yes. Got it all mixed up, was thinking m68k is same size as m4, and later somehow m68k became 8051 and gates transistors :(

That's better. 65K gates is probably close to 240K transistors. And an 8051 is probably close to 5K transistors, not 60K transistors.