Something seldom acknowledged is that mild variable-length instructions are not a new thing in RISC, and didn't start with Arm's Thumb2 -- or even with SuperH adding a few 32-bit instructions to their originally 16-bit one.
If we can agree that the essence of RISC is separating the instruction set into load and store instructions that don't do arithmetic (except incidentally in calculating the address), and instructions that do arithmetic only between registers, then the CDC6600 (1964) [1] and Cray-1 (1975) were RISC, and had 15&30 bit instructions and 16&32 bit instructions, respectively. The original experimental IBM 801 design (the 24 bit one) had two instruction lengths. Berkeley RISC-II had two instruction lengths.
Other than the very recent Aarch64, having a single instruction length was only a defining (supposedly) RISC characteristic between about 1985 and 1995, ten years out of 60 years of RISC history until now.
> A few selected software programs were compiled, __but not linked__, using GCC.
Unfortunately this artificially disadvantages RISC-V, where the compiler generates the maximum-size (multi-instruction) sequences for function calls and data references and the linker performs "relaxation" which only ever (and quite significantly) decreases code size and instruction count, especially for function calls where most functions can be reached with a single instruction with ±1 MB range.
Most other ISAs optimistically generate code with the smallest displacements, then the linker expands those with insufficient reach, which can itself cause some other instruction to have insufficient reach. This is especially problematic in ISAs with 8 bit (or smaller!) displacements.
In RISC-V the code starts out already correct, just larger than necessary and a single pass will get virtually all of the possible compaction.
Not linking means this isn't done at all.
[1] actually it was slightly funkier in that it didn't have explicit load and store instructions, but storing an address into a particular A register implicitly started a load or store of the same-numbered X register, depending on which register (and a couple of them did nothing).
If we can agree that the essence of RISC is separating the instruction set into load and store instructions that don't do arithmetic (except incidentally in calculating the address), and instructions that do arithmetic only between registers, then the CDC6600 (1964) [1] and Cray-1 (1975) were RISC, and had 15&30 bit instructions and 16&32 bit instructions, respectively. The original experimental IBM 801 design (the 24 bit one) had two instruction lengths. Berkeley RISC-II had two instruction lengths.
Other than the very recent Aarch64, having a single instruction length was only a defining (supposedly) RISC characteristic between about 1985 and 1995, ten years out of 60 years of RISC history until now.
> A few selected software programs were compiled, __but not linked__, using GCC.
Unfortunately this artificially disadvantages RISC-V, where the compiler generates the maximum-size (multi-instruction) sequences for function calls and data references and the linker performs "relaxation" which only ever (and quite significantly) decreases code size and instruction count, especially for function calls where most functions can be reached with a single instruction with ±1 MB range.
Most other ISAs optimistically generate code with the smallest displacements, then the linker expands those with insufficient reach, which can itself cause some other instruction to have insufficient reach. This is especially problematic in ISAs with 8 bit (or smaller!) displacements.
In RISC-V the code starts out already correct, just larger than necessary and a single pass will get virtually all of the possible compaction.
Not linking means this isn't done at all.
[1] actually it was slightly funkier in that it didn't have explicit load and store instructions, but storing an address into a particular A register implicitly started a load or store of the same-numbered X register, depending on which register (and a couple of them did nothing).